5.6 A 0.68nW/kHz supply-independent Relaxation Oscillator with ±0.49%/V and 96ppm/°C stability

RC Relaxation Oscillators (RxO) are attractive for integrated clock sources compared to LC and ring oscillators (RO), as LC oscillators pose integration challenges and RO designs have limited voltage and temperature (V-T) stability. RxOs generate a clock whose time period (TP) depends only on the timing resistor (R) and capacitor (C). Ideally, TP is independent of V-T; however, most RxOs use a reference voltage (VREF) against which the voltage of C (Vc) is compared. Generating a V-T independent VREF is non-trivial and causes variations in RxO frequency. A common approach is the use of VDD-independent current sources or band-gap or device-Vt based VREF [1]. The former are generally high-power options [2] while the latter is subject to process and V-T variations. A correct-by-design approach was adopted in [3] demonstrating VDD-independent operation by cancelling variations through differential sampling of VDD. Further, the power overhead of a supply-independent VREF is overcome by exploiting differential integrator virtual ground. However, 4V 2 /R power in the RC tank and high power VCO increase the energy/cycle. This work achieves supply-independence using VREF that is a fixed ratio of VDD. This scheme is shown Fig 5.6.1. VREF is generated using a small switched capacitor reference (SCR) such that VREF = VDD/3 (BY3). SCRs are relatively robust to temperature and switching frequency variations especially in the absence of large load currents as in this design. The conceptual waveforms in Fig 5.6.1 show VC while C is being discharged from VDD=0.9 and 1.5V to their corresponding BY3 voltages. Note that TP is dictated only by the RC elements and is independent of VDD. The power expended in the RC tank is reduced to 0.44V 2 /R giving substantial power savings. Simulation waveforms show how VDD-induced variations in comparator (X1) speed affect the RxO TP, highlighted by inset waveforms. The 0.9V curve crosses the BY3 trip point at the correct time but experiences a delayed trigger. Likewise, an early trigger at 1.5V results in shorter TP. To reduce this effect, X1 must be designed to have sufficient bandwidth at VDDmin which costs power [4]. However, this large bandwidth is only necessary at times when VC is very close to VREF. Observe that X1 is idle for VC>>VREF and can potentially be power gated if it can be turned ON in time for a precise comparison as VC approaches VREF. This sub-cycle duty cycling (SDC) of X1 significantly reduces energy/cycle …